1. Field of the Invention
The present invention relates generally to an apparatus for outputting complementary signals using bootstrapping technology, and, more particularly, to an apparatus for outputting complementary signals using bootstrapping technology, which can reduce a related area by improving the structures of a bootstrapping circuit block and the apparatus for outputting complementary signals and which can achieve high performance in low-power applications by increasing switching speed.
2. Description of the Related Art
As a result of the higher performance and diversification of portable electronic devices such as mobile phones, Personal Digital Assistants (PDAs) and Portable Multimedia Players (PMPs), the level of integration and operating frequency of circuits within the portable electronic devices are increasing, thereby resulting in an abruptly increasing power consumption.
The methods of design for minimizing the power consumption of digital CMOS circuits, the most effective method is to scale down supply voltage. The reason for this is that in most digital systems, power consumption is proportional to the square of supply voltage. However, since the operating speed of a digital CMOS circuit is closely related to the intensity of current, the method of lowering supply voltage may significantly decrease the operating speed of a system. Bootstrapping technology, which was proposed as a method for solving the above problem, is used to generate a voltage higher than a supply voltage by using capacitive coupling. This technology is effective in minimizing the problem of low performance although the supply voltage is lowered in order to reduce power consumption.
FIG. 1 is a diagram showing the construction of a conventional Bootstrapped Dynamic Logic (referred to as a ‘BDL’) for outputting one signal using bootstrapping technology. FIG. 2 is a diagram showing the construction of a conventional complementary signal output apparatus for outputting complementary signals using bootstrapping technology.
As shown in FIG. 1, the BDL using bootstrapping technology includes a bootstrapping circuit in a precharge node (which is a timing-critical path), so that the latency of the bootstrapping circuit is included in the net latency of a logic family. Accordingly, in the conventional BDL, parasitic capacitance is increased in a timing critical net because the size of an inverter must be large in order to drive a very large bootstrapping capacitor. Accordingly, a high switching speed cannot be expected. Furthermore, since the conventional BDL has a single-ended structure, as shown in FIG. 1, the construction of an XOR logic or a multiplexer logic requiring complementary inputs is restricted.
Accordingly, in order to input complementary signals to the XOR logic or multiplexer logic, a conventional differential-type logic circuit is constructed simply by connecting two BDLs 21 and 22, such as that shown in FIG. 1, to a precharged differential logic block 10, as shown in FIG. 2. However, since the conventional complementary signal output apparatus shown in FIG. 2 is configured simply by combining the two BDLs, such as that shown in FIG. 1, and is configured to output complementary signals, the entire area of the circuit is increased, so that it is difficult to use it for portable electronic devices.